IC Design

Design Service Model

Level 0 Prime :
Production Supporting Stage Spec feasibility to Sample

  • Spec Define/Verification
  • Test / IQ (Support Mass Production / Error Analysis)
  • Include Level 0

Level 1 :
Production Supporting Stage RTL Interface to Sample

  • Top Integration
  • Synthesis
  • RTL to Gate Equivalence Check
  • Function Mode STA
  • Clock Generation Module Design
  • DFT RTL Design
  • Include Level 1.5

Level 2 :
Production Supporting Stage Netlist Interface to Sample

  • Checking DFT Logic for Gate-level Netlist
  • Include Level 2.5

Level 3 :
Production Supporting Stage PG to Sample

  • Physical Verification
  • Design Preparation for Fab
  • Making Ebeam Data

Level 0:
Production Supporting Stage Spec Interface to Sample

  • Top Integration
  • Bus Architecture Design
  • System Level Verification
  • Test Firmware Suite
  • IP Design, IP Introduction, IP Verification
  • Block Design/Verification
  • FPGA System Design/Emulation
  • Include Level 1

Level 1.5:
Production Supporting Stage with DFT Netlist Interface to Sample

  • RTL Design For Test (Logic/Memory/IP/IO etc) Design
  • DFT Mode STA/Simulation
  • DFT Vector Generation
  • DFT to Gate Equivalence Check
  • Include Level 2

Level 2.5:
Layout to PG
(Pattern Generation)

  • Place & Route (P&R)
  • Manual(MOS Production), Mixed(Analog Production)
  • Physical Verification
  • Post Layout STA
  • Layout to Gate Equivalence Check
  • Include Level 3

Edge Service

SoC Support

  • Spec Definition for Mass Production
  • Top Integration for DFT
  • Suggestion Tech. Process

RTL Check

  • Linting & Optimization
  • Test Design Rule Check
  • Layout Guide

Design Review Organizer

  • Design Methodology Review
  • Pre-Layout Design Review
  • Post-layout Design Review

Synthesis for Timing Closure

  • Synthesis for Power Optimization
  • Static Timing Analysis
  • Equivalence Check

Auto P&R

  • Early Engagement
  • PowerPlan/FloorPlan
  • CTS/CTO
  • Chip Size Optimization
  • P&R
  • Timing Optimization

Design Review Organizer

  • Analog IC/IP
  • Digital CMOS Logic
  • Mixed Device
  • Memory Device
  • LDI
  • EEPROM

Design For Testability

  • Scan Design & ATPG
  • Memory BIST/BIRA
  • At-Speed Test Strategy

Verification & Post Processing

  • Multi-Power LVS
  • Physical Design Rule Check
  • Noise Analysis
  • IR-Drop/Rise Analysis
  • Bonding Rule Check
  • Antenna Rule
  • Check

Service Strength

Man Power capable of product development at the same time

  • Partner of Samsung Electronics Foundry
  • Building one stop support system (RTL to GDS handoff)
  • SoC / DFT dedicated team operation
  • Provide product optimization solution

Experience to do multiple stages/ projects

  • Provide high quality design service base on experiences
  • Experiences on develop 130nm~7nm
  • Progress Design Verification
  • Progress DFT Project

Perfect security operation

  • CCTV without blind spot
  • Separate internet/office according to customer
  • Security Guard 24/7
  • Seal and control all In and Out Device as Smartphone, USB…